NVIDIA Vera CPU speeds up chip design up to 1.5x in early EDA testing
NVIDIA is using its new Vera CPU to accelerate the design of future processors, achieving up to 1.5x performance gains in key electronic design automation (EDA) workloads.
- 1.5x
- 88
What Happened
NVIDIA is collaborating with Cadence and Synopsys to optimize EDA applications for its new Vera CPU. The company is already deploying Vera across workflows used to design its next-generation CPUs and GPUs, aiming to speed up simulation, verification, and implementation — stages that heavily depend on CPU performance. These stages are critical for validating designs and moving products toward tapeout.
1.5x
Early testing with Cadence Jasper and Synopsys VCS showed up to 1.5x higher performance using the same number of cores.
- Logic simulation
- Formal verification (e.g., Cadence Jasper)
- Digital implementation
- Regression testing
Vera combines 88 custom NVIDIA Olympus CPU cores with a high-efficiency LPDDR5X memory subsystem and second-generation NVIDIA Scalable Coherent Fabric. This architecture delivers strong per-core performance, high memory bandwidth, and consistent low latency — important for mixing latency-sensitive jobs with large-scale regression testing across compute farms.
NVIDIA plans to build on Vera with the next-generation Rosa CPU, powered by the Rigel core, while continuing to optimize leading EDA applications. The company is creating a continuous feedback loop between silicon design, software optimization, and systems engineering, with each generation helping build the next.
Why this matters
Chip design is increasingly complex, requiring years of validation. By deploying its Vera CPU in critical EDA workflows, NVIDIA aims to shorten design cycles and improve throughput. This could accelerate the pace of innovation in CPUs and GPUs, affecting everything from AI to consumer electronics.
Terms in This Story
- EDA
- Electronic design automation, software tools used to design electronic systems such as chips.
- formal verification
- A method to mathematically prove that a chip design meets its specifications.
- tapeout
- The final stage of chip design where the design is sent to manufacturing.
- RTL
- Register-transfer level, a high-level description of a chip's digital circuitry.
Summarised from the linked release; details can be imperfect — always verify against the original source.